Looking at the code issues of one of the students, I noticed a mystic issue with the simulator, so in sci_isr if you check TDRE bit first, even though the transmission interrupts gets disabled it looks like it doesn't actually clear the interrupts! However if you check for RDRF bit (see below) this issue doesn't happen
LDAA SCSR
BITA #RDRF
BNE SCI_RDRF
BITA #TDRE
BNE SCI_TDRE
Time permits, I'll try to further investigate to see what's the source of the problem; there may be a reasonable explanation for this(!), meanwhile please adjust your code as per above.
There was also a minor issue in the queue.asm code; sec/clc (setting/clearing the carry bit) must be called close to RTS, ensuring that other instructions will not alter the carry bit after it; here is the updated code: queue.asm
LDAA SCSR
BITA #RDRF
BNE SCI_RDRF
BITA #TDRE
BNE SCI_TDRE
Time permits, I'll try to further investigate to see what's the source of the problem; there may be a reasonable explanation for this(!), meanwhile please adjust your code as per above.
There was also a minor issue in the queue.asm code; sec/clc (setting/clearing the carry bit) must be called close to RTS, ensuring that other instructions will not alter the carry bit after it; here is the updated code: queue.asm
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